Synopsys USB Solution Passes USB-IF Certification

Synopsys has announced that its Designware Superspeed USB (USB 3.0) solution, including Controller and PHY IP, passed the USB Implementers Forum (USB-IF) Superspeed USB certification. To achieve certification, the IP must pass protocol, electrical and interoperability tests for Superspeed USB (USB 3.0, 5Gbps) and Hi-Speed USB (USB 2.0, 480Mbps). Synopsys created a fully integrated USB 3.0 IP solution, optimising all speed modes into a single USB 3.0 solution.

This implementation enables designers to reduce area, pin count and power compared to separate USB 2.0 and Superspeed USB-only designs. The integrated Designware Superspeed USB IP significantly lowers integration risk and effort by not requiring designers to manage two distinct USB 2.0 and USB 3.0 data paths in their system-on-chips (SoCs). Synopsys will be showcasing its certified Designware Superspeed USB IP solution at the Superspeed USB Developer's Conference in Taipei on 1-2 April, 2010. The USB device controller and PHY IP are based on Synopsys' technology Hi-Speed USB products, which have been silicon proven in thousands of designs.

Optimised for low power, the USB device controller is designed to allow designers to maximise battery life by using dual power rails. The Designware Superspeed USB PHY consists of integrated high-speed digital and analogue blocks, PLL and I/O pads, which are delivered as GDSII for advanced foundry processes. This saves designers considerable time, cost and the risk of acquiring and integrating the IP separately.

The Designware Superspeed USB Verification IP has built-in support for the VMM methodology, enabling designers to quickly verify connectivity between integrated IP and the SoC. The Linux drivers and System C transaction-level models in the Designware Superspeed USB virtual prototype allow designers to begin software development in parallel with IP integration, months before hardware and FPGA prototypes are ready. This significantly reduces the length of the product design cycle.

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