Synopsys Introduces Designware DDR Controllers

Synopsys' Designware Universal DDR Protocol and Memory Controllers both support the DDR2, DDR3, Mobile DDR and LPDDR2 SDRAM standards. The Designware Universal Memory Controller helps reduce both the latency and silicon area by up to 50 per cent compared with Synopsys' previous generations of DDR memory controllers, thus improving the DRAM interface performance and reducing overall chip costs. The Designware Universal Protocol Controller provides efficient DDR control and protocol translation for applications without the need for a multi-ported memory controller.

Both controllers deliver memory-system performance of up to 2133Mbps, the maximum data rate of the DDR3 standard, and offer a broadly utilised DFI 2.1-compliant interface to the DDR PHY. Furthermore, the Universal DDR Memory and Protocol Controllers enable designers to easily integrate multiple DDR interfaces into one design, servicing a range of products spanning applications such as consumer electronics, mobile, network computing and automotive, with lower risk and improved time to market.

The multi-port Designware Universal DDR Memory Controller accepts memory-access requests from up to 32 application-side host ports, each of which can be configured independently to be synchronous or asynchronous to the controller clock. In addition, the Designware Universal DDR Memory Controller provides high-memory bandwidth utilisation through transaction reordering, bandwidth allocation per port, and quality-of-service (QoS) based arbitration for latency-sensitive and/or high-bandwidth traffic.

Complementing the Designware DDR Universal Memory Controller, the single-port Designware Universal DDR Protocol Controller is designed to optimise memory-channel bandwidth utilisation with reduced latency, allowing designers to implement a custom memory scheduler that is optimised for specific DRAM traffic patterns. The Designware Universal DDR Protocol Controller supports 1:1 or 1:2 clock-frequency ratios between the controller and memory channel, enabling low latency in high speed, general-purpose process technologies and ease of timing closure in low-power process technologies.

The Designware Universal DDR controllers are part of Synopsys' Designware DDR IP offering, which consists of digital controllers and PHY IP supporting DDR, DDR2, DDR3, Mobile DDR and LPDDR2. The Designware DDR IP supports leading 130, 90, 65, 55 and 45/40nm technologies. Synopsys helps lower integration risk by providing high-quality DDR IP solutions that have been implemented in hundreds of applications and are shipping in volume production.


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