Icyflex Processor Cores Have Flexible Architecture
The Icyflex range of ultra-low-power 16/32-bit RISC processor cores developed by CSEM offers a flexible architecture that allows for different combinations of control and DSP functionality. Three silicon-proven cores are so far available, consuming as little as 6uW/MHz. The Icyflex architecture was developed as a flexible processor, with DSP and control-type capabilities and C-compiler support. A high level of flexibility allows the architecture to be optimised for the application, ranging from simple control-type through to highly parallel audio/video signal-processing applications.
Three variants are available: Icyflex1 - a 16/32-bit RISC processor for a mix of control and DSP-type applications, such as wireless sensor networks requiring local signal processing; Icyflex2 - a smaller 16/32-bit RISC processor for control type applications with power consumption as low as 6uW/MHz (in 65nm LP CMOS); and Icyflex4 - with a scalable architecture capable of some control and massive parallelism for computation-intensive DSP-type applications such as audio or video processing.
All three processors are available as VHDL soft blocks with multiple parameters (bus widths, stack size, optional blocks) so that only the part of the processor useful for the application is integrated. The processors can be configured at run time to add new addressing modes and new instructions to reduce the number of cycles for individual algorithms. The processors feature powerful data paths (up to 36 multiply-and-accumulate units) and high bandwidth buses to registers and memory for maximum throughput per instruction, or clock cycle.
The processors are designed for testability and On-Chip-Debug support through a JTAG interface. Development tools are available, based on the GNU tool suite (compiler, assembler, debugger, cycle-accurate instruction-set simulator) with plug-in for the Eclipse IDE. All Icyflex processor cores are available as IP cores under licence, or as part of a low-power SoC design at CSEM. CSEM will be demonstrating the Icyflex at the Embedded World exhibition in Nuremburg on 2-4 March.
Three variants are available: Icyflex1 - a 16/32-bit RISC processor for a mix of control and DSP-type applications, such as wireless sensor networks requiring local signal processing; Icyflex2 - a smaller 16/32-bit RISC processor for control type applications with power consumption as low as 6uW/MHz (in 65nm LP CMOS); and Icyflex4 - with a scalable architecture capable of some control and massive parallelism for computation-intensive DSP-type applications such as audio or video processing.
All three processors are available as VHDL soft blocks with multiple parameters (bus widths, stack size, optional blocks) so that only the part of the processor useful for the application is integrated. The processors can be configured at run time to add new addressing modes and new instructions to reduce the number of cycles for individual algorithms. The processors feature powerful data paths (up to 36 multiply-and-accumulate units) and high bandwidth buses to registers and memory for maximum throughput per instruction, or clock cycle.
The processors are designed for testability and On-Chip-Debug support through a JTAG interface. Development tools are available, based on the GNU tool suite (compiler, assembler, debugger, cycle-accurate instruction-set simulator) with plug-in for the Eclipse IDE. All Icyflex processor cores are available as IP cores under licence, or as part of a low-power SoC design at CSEM. CSEM will be demonstrating the Icyflex at the Embedded World exhibition in Nuremburg on 2-4 March.
Comments