MSC Promotes LatticeECP3™: First PCIe 2.0 Compliant Low Cost FPGA

LatticeECP3™ is the first and only PCI Express 2.0 compliant low-cost FPGA. The PCI Express 2.0 specification allows operation at a lower speed than PCI Express 1.1 (2.5 Gbps), but the loop bandwidth characteristics are different and more rigorous.

Now designers who need PCI Express 2.0 compliance, but do not need the PCI Express link to operate at 5 Gbps, can use the low-cost LatticeECP3 FPGA in PCI Express 2.0 compliant systems. The PCI SIG PCI Express 2.0 Integrators List has been updated to include the LatticeECP3 x4 endpoint IP. As a subset of the x4 endpoint IP, the LatticeECP3 x1 endpoint IP is also qualified.

LatticeECP3 PCI Express Evaluation Platforms

A number of hardware platforms are available to help designers evaluate and develop with the LatticeECP3 PCI Express solution. All platforms feature:

  • Compliant to PCI Express 2.0 endpoint
  • PCI SIG Compliance Workshop certified
  • Soft Physical, Data Link and Transaction layers, and 4 KB data payload size
  • Low LUT usage (5K LUTs) PCI Express x1 configuration
  • Reference design to support TLP termination, interrupts, ingress/egress datapath and WISHBONE bus interface

The LatticeECP3 Versa Development Kit and LatticeECP3 PCI Express Development Kit combine application-specific evaluation boards, evaluation PCI Express IP, relevant reference designs and host software and drivers in one comprehensive package. The LatticeECP3 Serial Protocol Board allows designers to quickly and seamlessly evaluate the Lattice PCI Express Solutions portfolio, and to use it as a basis for their own PCI Express development.


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