Altera Unveils Innovations at 20 nm
Altera’s 20-nm mixed-system fabric includes the integration of 40-Gbps transceiver technology, a next-generation variable-precision digital signal processing (DSP) block architecture that delivers over 5 TFLOPs of IEEE 754 floating-point performance, and heterogeneous 3D ICs that integrate FPGAs with a user-customizable HardCopy® ASIC or a variety of other technologies, including memory, third-party ASICs and optical interfaces through an innovative high-speed interface. Altera is the only company in the industry able to integrate FPGAs with ASICs into a single device.
The 20-nm mixed-system fabric also offers continued innovations in power management, including adaptive voltage scaling, Programmable Power Technology, and optimized process technology, which enable Altera to reduce device power consumption up to 60 percent compared to its previous generation of devices.
Development of heterogeneous 20-nm systems are supported through a full-featured, high-level design environment that includes system-level design tools (Qsys), C-based design tools (OpenCL™) and DSP development software (DSP Builder). Altera continues its focus on designer productivity by scaling its development tools to deliver the industry’s fastest compile times at 20 nm.
“Designers of next-generation communications, networking, broadcast and computing applications are faced with the ever-increasing need for expanded bandwidth, higher performance and lower power,” said Bradley Howe, senior vice president of research and development at Altera. “Our innovations at 20 nm allow us to deliver a highly efficient, highly flexible mixed-system fabric that features optimal levels of dedicated circuitry with the latest 20‑nm FPGA process technology. The result is a device that delivers the industry’s highest levels of IC integration, performance and bandwidth at the lowest power.”
Altera’s next-generation devices leverage TSMC’s 20-nm process technology and include the industry’s highest levels of system integration, including a hard ARM® processor subsystem. 20-nm system-on-chip (SoC) FPGAs provide customers a software migration path from 28 nm to 20 nm while delivering a 50 percent processor subsystem performance increase.