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Cypress Adds 16-Mbit Parallel nvSRAMs and Synchronous NAND Interfaces to Industry-Leading Non-Volatile Memory Portfolio

Cypress Semiconductor Corp. (Nasdaq: CY) today introduced a family of 16-Mbit non-volatile static random access memories (nvSRAMs), including devices with synchronous NAND flash memory interfaces. The family marks the industry’s first non-volatile SRAM memory that can interface directly with Open NAND Flash Interface (ONFI) and Toggle NAND bus controllers. The 16-Mbit family extends Cypress's nvSRAM portfolio to address Solid State Drives (SSD) for enterprise systems, high-end Programmable Logic Controllers (PLC), high-speed data/error loggers in storage, and networking equipment.

The 16-Mbit nvSRAMs offer access times as low as 25 ns, making them the fastest asynchronous non-volatile RAMs on the market. The new devices are offered with an optional integrated Real-Time Clock (RTC) that is not available in competing solutions. The RTC enables time-stamping of critical data to be logged. Cypress nvSRAMs feature infinite read, write and recall cycles, with 20-year data retention, making them the best solution for applications requiring continuous high-speed writing of data and absolute non-volatile data security.

“The new 16-Mbit family pushes the envelope of speed, density, and performance while delivering the same superior reliability that is the hallmark of our nvSRAM portfolio,” said Babak Taheri, Vice President of the Non-Volatile Products Business Unit at Cypress. “The synchronous NAND interfaces open multiple new markets to Cypress nvSRAMs and add to the breadth and flexibility of our overall non-volatile offerings.”

The ONFI NAND interface nvSRAM supports the ONFI 3.0 NV-DDR interface (100MHz) and the ONFI 3.0 NV-DDR2 interface (200MHz). The Toggle NAND interface nvSRAM is compatible with Toggle 2.0 NAND controllers for DDR operation at 200MHz.

Both ONFI and Toggle versions support single-channel operations in x8 and x16 data bus widths, and dual- and quad-channel operations in x8 bit data bus width, which allows operations of up to 400 million transactions per second.

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