Xilinx Integrated Block for the PCI Express Gen3 Standard Accelerates Productivity and Increases System Performance
With a 40 percent performance advantage versus competing memory solutions, Xilinx allows users to accelerate productivity by offering maximum memory data rates in its mid-speed grade devices as well as built-in capabilities in its Virtex-7 XT devices for single-root I/O virtualization and multi-function end points to address the emerging needs in Data Center and cloud computing.
"Customers have the components they need to implement high-performance PCI Express x8 Gen3-based designs at the lowest BOM cost by using a mid-speed grade device," said Ketan Mehta, Xilinx PCI Express Product Manager. "In addition, Xilinx enables the highest productivity levels with industry-leading transceiver technology that provides automated tuning capabilities to quickly bring up a functioning link, including auto-adaptive Decision Feedback Equalization (DFE). This dramatically accelerates development time by simplifying the set up and use of the high-speed serial transceivers that support the PCI Express Gen3 standard."
Virtex-7 XT and HT FPGAs are the first generation of Xilinx All Programmable devices that integrate hard IP cores for the PCI Express Gen3 standard. Both Kintex™-7 and Virtex-7 FPGAs feature1866 Mb/s DDR3 external memory interfaces to further bolster the PCI Express system throughput. Xilinx's PCI Express Gen3 video demonstrates the integrated block operating on a Virtex-7 X690T FPGA with an off-the-shelf PCI Express Gen3 system.
For designs that do not use an integrated block for the PCI Express Gen3 standard, soft IP core support is available through Xilinx Alliance Program members, including Northwest Logic and PLDA.