24nm e-MMC Boosts Performance, Reduces Costs, Makes Large Densities a Viable Option for Space-Conscious Devices
Toshiba's 24nm e-MMC process lowers costs, enables higher densities, boosts performance and allows for smaller packages – all of which are key requirements for space-conscious applications such as smartphones, tablet PC s, eBooks, digital video cameras, printers, servers, and POS systems.
Integrating up to 128GB NAND and an e-MMC controller in a single package, Toshiba's new family of 24nm e-MMC devices combine up to 16 pieces of 64Gbit (equal to 8GB) NAND chips fabricated with Toshiba's cutting-edge 24nm process technology. Toshiba was the first company to succeed in combining 16 pieces of 64Gbit die in e-MMC to achieve 128GB of memory by applying advanced chip thinning and layering technologies to realize individual chips that are only 30 micrometers thick. Full compliance with the JEDEC e-MMC Version 4.41 (V4.41) standard for embedded MultiMediaCards supports standard interfacing and simplifies product design-in, reducing development burdens on product manufacturers.
“The utilization of our new toggle-mode DDR NAND die at 64Gbit density is key to enabling our e-MMC to support the higher performance, and smaller, thinner packages that customers desire,” noted Scott Beekman, senior business development manager, mobile communications memory for TAEC. “For example, our 128GB e-MMC can now be supported in a smaller 14 x 18 package, which many space conscious applications can support.”
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