CADEKA Introduces Industry’s Lowest Power Octal ADCs
The CDK8307 employs internal reference circuitry, a serial control interface, and serial LVDS output data. Both 12-bit and 14-bit LVDS output modes are available and selected through an SPI control interface. These converters utilize proprietary pipeline architecture to offer the industry’s best power/performance ratio and are designed to easily interface with field-programmable gate arrays (FPGAs) from several vendors.
“At 50MSPS, the power dissipation is 40mW per channel. That’s over 30% lower power than the closest competitor in its class,” explains Jay Dokter CADEKA’s Vice President of Sales and Marketing. “Our CDK8307 is pin compatible to many devices on the market today, allowing designers of portable imaging applications to easily and significantly reduce their system power consumption without sacrificing performance or image quality.”
For additional power savings, the CDK8307 includes Power Down and Sleep Modes that drop the power consumption to <10µW and 3mW per channel respectively. In addition, the unprecedented wake-up times (18µs from Power Down and 0.5µs from Sleep) of the CDK8307 allow system designers to switch off the ADC during idle modes, reducing the system’s average power dissipation.
In addition to ultra-low power, the CDK8307 offers excellent noise performance. At 14-bits and 50MSPS, the CDK8307 outperforms the competition with 72.5dB signal to noise ratio (SNR) and 80dB spurious free dynamic range (SFDR). This unique power/performance combination makes the CDK8307 well suited for portable ultrasound equipment and a wide variety of applications in the medical, instrumentation, and communication markets.
An easy to use evaluation board is available to allow fast and cost-effective evaluation, shortening the design process.