IP Core Suitable for Broadcom-Inclusive Networks
Lattice Semiconductor has announced the immediate availability of the HiGig MAC IP core for its low-cost LatticeECP3 FPGA range, for interconnecting multiple devices to operate as one logical network. Providing features such as quality of service (QoS), mirroring and link aggregation, the new Lattice IP core will allow designers to implement low-cost networks using Broadcom devices. The HiGig MAC ensures that the Media Access rules specified in the 802.3ae IEEE standard and HiGig Protocol definitions are met while transmitting a frame of data over Ethernet.
On the receiver side, it extracts the different components of a frame and transfers them to higher applications through a FIFO interface. Compliant with Broadcom HiGig and HiGig2 protocol definitions, the HiGig MAC IP core has a 64-bit wide internal data path operating at a maximum frequency of 156MHz on the LatticeECP3 FPGA. The core provides XGMII and XAUI interfaces to the PHY layer and supports variable-sized packet transmission with fixed-sized messaging capability (HiGig2 only).
With multicast address filtering and 16-bit statistics counters, the core requires approximately 4,100 FPGA look-up tables (LUTs) for HiGig implementations and approximately 4,700 FPGA LUTs for HiGig2 implementations. Included as a standard feature in the Lattice Diamond design environment, the IPexpress module reduces design time by allowing IP parameterisation and timing analysis on the designer's desktop.
This allows users to customise Lattice's extensive library of IP functions for their individual applications, integrate them with their proprietary FPGA logic designs and evaluate the overall device operation via simulation and timing analysis prior to making any IP purchase commitments. The HiGig MAC IP core is available now and can be ordered through Lattice sales at the list price of $5,000 (?3,206).
On the receiver side, it extracts the different components of a frame and transfers them to higher applications through a FIFO interface. Compliant with Broadcom HiGig and HiGig2 protocol definitions, the HiGig MAC IP core has a 64-bit wide internal data path operating at a maximum frequency of 156MHz on the LatticeECP3 FPGA. The core provides XGMII and XAUI interfaces to the PHY layer and supports variable-sized packet transmission with fixed-sized messaging capability (HiGig2 only).
With multicast address filtering and 16-bit statistics counters, the core requires approximately 4,100 FPGA look-up tables (LUTs) for HiGig implementations and approximately 4,700 FPGA LUTs for HiGig2 implementations. Included as a standard feature in the Lattice Diamond design environment, the IPexpress module reduces design time by allowing IP parameterisation and timing analysis on the designer's desktop.
This allows users to customise Lattice's extensive library of IP functions for their individual applications, integrate them with their proprietary FPGA logic designs and evaluate the overall device operation via simulation and timing analysis prior to making any IP purchase commitments. The HiGig MAC IP core is available now and can be ordered through Lattice sales at the list price of $5,000 (?3,206).
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