Key features and benefits of the LMK04906
- Maximum flexibility: Integration of seven high-performance, programmable outputs offered in LVDS, LVPECL and LVCMOS simplifies timing design.
- Integration reduces BOM costs: High integration eliminates the need for the oscillators and clock buffers typically used to implement a low-jitter clock tree. Features such as holdover, input switching, analog/digital delay, and odd/even dividers increase clocking functionality while reducing cost.
- Industry's lowest jitter and phase noise: 100 fs RMS jitter from 12 kHz to 20 MHz with a noise floor of -160 dBc/Hz at 156.25 MHz output frequency enables greater signal integrity in high-speed data communication links such as 10GbE, FC, FCoE, and SAS/SATA.
The LMK04906 and CDCM6208 can be combined with the following devices to create a high-speed data link: TMS320C66x KeyStone Multicore DSP, LMK00301 3-GHz differential fanout buffer, LMK03806 clock generator with 14 outputs, DS100DF410 10GbE quad-channel retimer, LP3878-ADJ 800-mA low-noise LDO regulator, and TLK10002 dual-channel 10-Gbps multi-rate transceiver.