IP Cores Targeted At Video Security Applications

Lattice Semiconductor and Helion have released intellectual property (IP) cores for the video security and surveillance camera market. Targeting the LatticeXP2, LatticeECP2M and LatticeECP3 FPGA ranges, Helion has demonstrated its IONOS video pipeline IP and Vesta evaluation platform. The Helion Vesta evaluation platform is completely self contained and enables the development and realisation of image pipelines for camera systems, particularly in tight form-factor video security applications such as network IP and dome cameras.

Helion's Vesta modular technology platform combines a video processing baseboard, an image sensor and a Lattice field-programmable gate array (FPGA) capable of supporting a range of IONOS video pipelines. Helion offers a selection of video pipelines, ranging from basic to advanced monochrome and colour pipelines to high-resolution advanced high-dynamic-range imaging (HDRI) colour pipelines. Depending on the pipeline selected, it will consist of a number of individual video processing IP cores, such as defective pixel correction, logic-efficient 3 x 3 De-Bayering, high-quality 5 x 5 De-Bayering, colour-correction matrix, gamma correction, auto exposure and auto white balance.

These cores also support Lattice FPGA devices and all are compatible and connected using the Wishbone bus. Dr Arndt Bussmann, chief technical officer at Helion, said: 'LatticeXP2, ECP2M and ECP3 FPGAs support several image pre-processing functions for a number of image sensors from VGA to 12MP. 'The Wishbone bus makes it easy to combine and connect our various IONOS IP cores according to customer needs.

'That makes it easier to link different IP cores with each other and to use the appropriate FPGA, ranging from a small XP2 FPGA for a simple pre-processing unit, such as monochrome VGA with our Fast Auto Exposure, up to an ECP2M or ECP3 FPGA with full HD or 12MP colour pipe, including HDR. 'This combination of the Lattice FPGA, the Wishbone architecture and our IONOS IP cores is a very effective way to get an economical and customised image processing unit,' added Bussmann. Niladri Roy, Lattice senior product marketing manager, said: 'Helion's HDR IP is capable of supporting 1080p60, up to 12MP sensors, delivering full HD, and protects the customer's investment.

'It delivers quality at reduced system cost by eliminating the need for an external frame buffer, with the entire Image Signal Processing Pipeline, including HDR, implemented in streaming mode through the Lattice FPGA. 'Helion's auto-exposure IP is one of the industry's fastest for HDR sensors, executing within three frames, with no visible display bloom or blackout. 'Working with an Aptina A-1000 image sensor, Helion IP can deliver a scene dynamic range of 120dB and a system dynamic range up to 170dB, exceeding the requirements of both security and surveillance and automotive camera manufacturers,' added Roy.

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