Remote Radio Head For Wireless Infrastructure

Lattice Semiconductor has partnered with Affarii Technologies to demonstrate a low-cost, low-power remote radio head solution at 1,300mW per antenna for wireless infrastructure manufacturers. The integration of all remote radio head (RRH) processing has been achieved on a single Lattice ECP3-150 device, part of the LatticeECP3 FPGA family. The single-chip solution supports 2x2 Mimo configurations for WCDMA, LTE and Wimax applications and is part of an overall RRH hardware evaluation platform jointly developed by Lattice and Affarii.

The platform is comprised of the RF front-end, high-speed data conversion devices and the digital signal processing portion. The functionality of the full signal path package includes DDC/DUC, DPD, CFR and CPRI IP cores, supports multi-carrier waveforms up to 20MHz bandwidth and is compatible with Class AB and Doherty amplifiers using LDMOS and GaN transistors. All features of this RRH solution, both hardware and soft IP, are fully integrated and supported by Lattice's latest generation of design tools.

The RRH solution is built using Affarii's digitalTRX technology that includes Digital Up/Down Converter (DUC/DDC), Crest Factor Reduction (CFR) and Digital Pre-Distortion (DPD) functionality. When used with industry standard Doherty amplifiers the DPD solution provides up to 30dB of ACLR correction with PA output efficiencies exceeding 40 per cent, allowing flexible and efficient RRH designs. The solution is fully customisable, with end applications including WCDMA, LTE, Wimax, and DVB-T/S/H.

The RRH solution is supported by a development and test environment that includes GUI-based design simulation, performance analysis and a production test API with design examples. The LatticeECP3 family provides five logic density points between 17K and 150K LUTs. Embedded memory capacity ranges from 0.7 to 6.8 Megabits of dual-port block RAM with general-purpose I/O ranging from 133 to 586 I/O. Each device features both analogue PLLs and digital DLLs for optimum clock flexibility.

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