IR’s Versatile Family of CHiL Digital PWM Controllers Delivers Smallest Footprint; Highest Efficiency Multiphase Solutions
These new third generation CHiL devices offer efficiency shaping features such as phase shedding and variable gate drive with enhanced algorithms including PID scaling (when shedding phases) and phase current balancing to ensure maximum efficiency. The solution architecture supports the extremely high di/dt transients from high-end processors, and, as a result of a new Adaptive Transient Algorithm (ATA), the transients can be met with fewer phases and fewer capacitors to shrink system size.
“By offering the highest efficiency and smallest footprint, the new CHiL line-up continues to underline IR’s leadership position in providing versatile VR solutions for leading-edge CPU and GPU designs for servers, motherboards and graphics cards. Supporting designs from 1 to 8 phases, the new family offers flexible phase configurations that allow customers to vary the number of phases on each voltage loop to optimize cost and efficiency for each load,” said Deepak Savadatti, Vice President and General Manager, IR’s Enterprise Power Business Unit.
The new CHiL digital PWM controllers feature a 30 percent reduction in operating current to help meet higher efficiency goals during low-load operation. For protection of high-end circuits, the devices offer improved pulse-by-pulse current limit protection, controlled pulse width limiting a new phase imbalance/phase missing fault feature.
The devices fully support phase doubling using IR’s IR3598 to drive two phases from each PWM output. The devices also sense 12V, 5V and 3.3V supplies without special sequencing and feature PMBUS telemetry.
When designed with IR’s DirectFET® power MOSFETs and PowIRstage® integrated devices, the CHiL product line enables smaller solutions by combining the density advancements of DirectFET and PowIRstage. The highly digital nature of these devices enables extremely low pin count solutions in a 0.4mm pitch QFN packages, and an improved transient response that eliminates at least one SP bulk capacitor and many ceramic capacitors to deliver the smallest and most efficient solution.