Lattice and Oregano Introduce FPGA System IP Core
Lattice Semiconductor and Oregano Systems have launched three versions of the IEEE-1588 Timing Node System IP core for the LatticeECP3 and LatticeECP2M FPGA ranges. The SoC-class versions of the IP core are characterised by different levels of functionality and performance. The deterministic and lossless delivery of packets over a network has become a key requirement in Carrier Ethernet, Data Center Ethernet and Industrial Ethernet applications that demand precise synchronisation.
The baseline implementation is a single instance of the System IP core that contains a complete hardware and software implementation. The hardware is capable of handling arbitrary clock frequencies while allowing for robust clock state and rate synchronisation. Both analogue and digital PLL control loops are supported. Additionally, an optimised embedded implementation of the 8051 microcontroller enables a small-footprint implementation of the Precision Timing Protocol. Furthermore, the System IP core supports remote configuration and management via IEEE-1588 Management Messages, including in-field upgrades that enable the customer to use it either as a standalone SoC implementation or as a System IP Core along with the customer's mission logic.
An extensive test bench can be provided by Oregano upon request. A Dual instance version of the System IP core is also available. In this version, one instance acts as a PTP master and the other as a PTP slave with different profiles. A multi-core implementation of the 8-bit microcontroller is supported by sharing the program ROM and only one external oscillator is required for both ports, reducing the total solution cost. If a higher message rate - up to 10K messages per second - is required then the Dual HP (high performance) version of the IP core addresses this requirement. The Sync message generation for every client has been moved from software into hardware, reducing the 8051 microcontroller load to just the configuration and control of the packet engine.
The baseline implementation is a single instance of the System IP core that contains a complete hardware and software implementation. The hardware is capable of handling arbitrary clock frequencies while allowing for robust clock state and rate synchronisation. Both analogue and digital PLL control loops are supported. Additionally, an optimised embedded implementation of the 8051 microcontroller enables a small-footprint implementation of the Precision Timing Protocol. Furthermore, the System IP core supports remote configuration and management via IEEE-1588 Management Messages, including in-field upgrades that enable the customer to use it either as a standalone SoC implementation or as a System IP Core along with the customer's mission logic.
An extensive test bench can be provided by Oregano upon request. A Dual instance version of the System IP core is also available. In this version, one instance acts as a PTP master and the other as a PTP slave with different profiles. A multi-core implementation of the 8-bit microcontroller is supported by sharing the program ROM and only one external oscillator is required for both ports, reducing the total solution cost. If a higher message rate - up to 10K messages per second - is required then the Dual HP (high performance) version of the IP core addresses this requirement. The Sync message generation for every client has been moved from software into hardware, reducing the 8051 microcontroller load to just the configuration and control of the packet engine.
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