Cadence Improves Virtuoso IC Design Platform

Cadence Design Systems has announced performance, capacity and usability enhancements to its Virtuoso IC design platform. The improvements in Virtuoso IC6.1.4 are said to reduce overall design time while ensuring quality production ICs. This is said to benefit design teams working along the full spectrum of design complexity, from the most advanced-node designs to more traditional chips. The Virtuoso release has been extended to work efficiently at advanced nodes down to 28nm and now supports 64-bit processing for improved capacity and performance.

The Virtuoso Space-Based Router has been integrated into the Virtuoso Layout Suite cockpit, making it easier to access. It now provides design teams a single common router they can use from start to finish to help ensure consistent results. Additional time-saving, quality-enhancing updates have been made to the Virtuoso Analog Design Environment XL, and Cadence design constraints technology. Integrating the Virtuoso Space-Based Router into the Virtuoso Layout Suite brings the power of a net-capable router to the desk of every layout engineer.

Interactive wire editing and full chip automatic finish routing share the same algorithms, providing a flow for a higher quality of design, from IP module creation though full chip sign-off. Improvements to the Virtuoso Analog Design Environment XL include display capabilities within the product that can now produce more and better datasheets. The Virtuoso Analog Design Environment's ability to analyse multiple tests simultaneously, including those across corner and statistical variations, helps engineers pick the best circuit design directions early on and verify those choices efficiently post implementation.

The Cadence design constraints methodology, which can help engineers reduce layout optimisation and design refinement times by as much as 20 per cent, received a boost in the new release, with enhancements that make it easier to add design constraints. In addition, there are new design constraints specifically geared to address sub-45nm design yield challenges. The release extends the Cadence ExpressPcells capability to support multiple-user sites.

Now customers can use their vast libraries of Skill-parameterised cells anywhere and see up to an eight times performance improvement. Cadence also improved the analogue display technology to handle multi-gigabyte waveform files more efficiently. The company has removed the two-gigabyte limit on waveform databases to account for today's larger, more complex designs. Performance has also been boosted for underlying design rule engines.

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